VLSI Physical Design & STA Faculty (Part-Time)

<p>Job Description – Part-Time VLSI Physical Design & STA Trainer</p><p><strong>Organization:</strong> Physics Wallah (PW)</p><p><strong>Job Type:</strong> Part-Time</p><p><strong>Work Mode:</strong> Online</p><p>About the Role</p><p>Physics Wallah (PW) is looking for an experienced <strong>VLSI Backend Faculty / Trainer</strong> to train freshers for placement opportunities in Physical Design and Static Timing Analysis (STA). The ideal candidate should have strong hands-on industry experience, expertise in Synopsys tools, and the ability to explain complex technical concepts through practical examples and real-world design flows.</p><p>Key Responsibilities</p><ul><li>Teach VLSI Physical Design, Static Timing Analysis (STA), and physical verification concepts in a structured, easy-to-understand manner.</li><li>Conduct hands-on lab sessions using Synopsys tools and industry-relevant design flows and scripts.</li><li>Develop and update course curriculum, presentations, lab exercises, assignments, and quizzes based on current industry requirements.</li><li>Guide students through backend design projects and practical implementation exercises.</li><li>Conduct mock interviews and prepare students for VLSI backend placement opportunities.</li><li>Conduct regular doubt-clearing sessions and monitor student progress.</li><li>Collaborate with the team to enhance learning outcomes and improve student placement readiness.</li></ul><p>Required Skills & Experience</p><ul><li>Minimum <strong>3 years of hands-on experience in VLSI Backend / Physical Design</strong>.</li><li>Strong understanding of the complete RTL-to-GDSII flow, including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, timing ECO, and signoff.</li><li>Proficiency in Synopsys tools: Fusion Compiler (FC), PrimeTime (PT), Design Compiler (DC), ICC2, StarRC, and IC Validator (ICV).</li><li>Knowledge of Calibre for DRC/LVS is an added advantage.</li><li>Strong understanding of STA, setup and hold fixing, OCV/AOCV, crosstalk, IR drop, electromigration (EM), and low-power design using UPF.</li><li>Good TCL scripting and Linux skills.</li><li>Experience with tapeout at 28nm or below is preferred.</li><li>Excellent communication skills in <strong>English and Hindi</strong>.</li><li>Ability to explain technical concepts clearly and train freshers for industry requirements.</li></ul><p>Preferred Candidate Profile</p><ul><li>Working professionals with relevant VLSI industry experience.</li><li>Candidates with practical exposure to Physical Design, STA, and signoff activities.</li><li>Professionals interested in part-time teaching, mentoring, and placement-oriented training.</li></ul><p>Why Join PW?</p><ul><li>Opportunity to share industry expertise with aspiring VLSI professionals.</li><li>Contribute to practical, industry-aligned learning and placement preparation.</li><li>Be part of a growing technical education initiative.</li></ul><p><strong>Interested candidates</strong> can apply by sharing their updated resume and relevant industry experience.</p>

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